Programmed logic arrays (PLAs) are often incorporated in semiconductor integrated circuits used in data processing systems. A PLA performs logic computations or transformations, that is, it processes data by delivering data signal outputs as determined by data signal inputs in accordance with a prescribed logic computation or transformation rule.
A PLA typically has two main portions or planes, known as the AND plane and the OR plane, respectively. Outputs of the AND plane are inputs to the OR plane; and some of the outputs of the OR plane are fed back as inputs to the AND plane, so that the PLA implements a finite state machine. Each plane is in the form of a crosspoint logic array, that is, a rectangular array of intersecting row lines and column lines. Each plane is programmed in that at each crosspoint intersection of a row line with a column line, a separate driver transistor is connected or not, depending upon the desired logic function or transformation of that plane. Each of the input and output data signals of the plane can be a LOW or a HIGH voltage, corresponding to binary digital (1's and 0's) data signals entering into and emanating from the plane.
Basically, each plane of a PLA is designed to perform NOR logic functions of selected inputs thereto in accordance with the desired logic function or transformation of the inputs entering that plane, as described in greater detail below. The specifics of the NOR functions implemented by each of the planes are determined by the configurations in the respective planes of the presences versus absenses of the crosspoint driver transistors at the various crosspoints.
More specifically, in a PLA, inputs to a given plane thereof are applied along parallel (row) input lines (wires) to the gate electrodes of the driver transistors in the logic array corresponding to that plane, and outputs from the plane emanate along parallel (column) output lines orthogonal to the input lines. In one particularly useful form, each logic plane of a PLA is configured as a single stage of pseudo-NMOS logic. That is, each input line is connected to the gate electrode of each of the driver transistors (all n-channel MOS) that are present at crosspoints of that input line; each output line is connected through the source-drain path of a separate p-channel MOS precharge pullup transistor to a first power supply line (V.sub.DD) and is also connected through the source-drain paths of each of the driver transistors (that are present at crosspoints of that output line) in series through the source-drain path of an n-channel MOS pulldown transistor to a second power supply line (V.sub.SS). During the precharge phase of a given plane during each PLA cycle of operation, the pullup transistors are turned on while the pulldown transistor is turned off, whereby all the output lines are charged to the voltage (V.sub.DD) of the first power supply line; and during each evaluation phase immediately succeeding the precharge phase, the pullup transistors are turned off while the pulldown transistor is turned on, whereby each output line does or does not discharge to the voltage (V.sub.SS) of the second power supply line, depending upon whether or not any of the driver transistors present at crosspoints of that output line is then on.
During each cycle of the PLA operation, in order to supply inputs to the AND plane during appropriate time intervals of each cycle, an input register controls the flow of the inputs into the AND plane; similarly, in order to supply outputs from the OR plane to the rest of the system, as well as feedback to the AND plane during appropriate time intervals, an output register controls the flow of outputs from the OR plane.
The input and output registers, as well as the AND and OR planes, operate in accordance with an orderly control timing sequence. For timing purposes in a synchronous data processing system, suitable clock pulse timing sequences can be delivered to the registers, as well as to the AND and OR planes, in order to ensure this orderly timing of operation. Thus, the registers, as well as the planes, can operate to receive, as well as to deliver, new data signals during appropriate phases of each cycle of the clock. Thus, for example, during a first phase of each such cycle the input register by the AND plane, during a second phase the AND plane generates new corresponding data for propagation to and reception by the OR plane, during a third phase the OR plane generates new corresponding data for propagation to and reception by the output register, and during a fourth phase the output register receives the new data from the OR plane for propagation to other parts of the system as well as for propagation as feedback to the input register.
The duration of each of the pulses which enables the input register to be transparent--i.e., to receive fresh data--is ordinarily equal to the duration of each of the pulses which enable the output register to be transparent, but each pulse is applied to the input register during a different portion (first phase) of the cycle from that (fourth phase) during which each pulse is applied to the output register. Thus, the first and fourth phases are equal in time duration, but are not coincident.
In general, there is at least one output line of the OR plane to which so many crosspoint transistors are connected that the resulting response time delay of such output line is so long (owing to crosspoint transistor capacitance loading) that it is necessary for the fourth phase to succeed (rather than coincide with) the third phase. Thus, in general, the first, second, third, and fourth phases are successive phases. The time durations of all such phases are advantageously mutually equal, moreover, for simplicity of design of the circuitry that supplies the control timing for these phases.
In a variety of data processing contexts it is desirable to perform further logic transformations upon the output data emanating from the OR plane of a PLA before delivering the data to other parts of the system, such as to the ALU (Arithmetic Logic Unit), or before feeding back the data to the AND plane. In U.S. Pat. No. 4,339,516, issued to Blahut et al on Aug. 16, 1983 entitled "Stored-Program Control Machine," a single logic gate--specifically a static (unclocked) AND gate--was inserted in each of the feedback lines of a given PLA to receive data from the PLA output register, as well as data from one or more other PLAs in the data processing system, and to process and deliver data back to the PLA input register. In that manner, some additional data processing capability was added to the PLA. The amount of such additional processing on each line, however, is limited because of the need for the data emanating from the added logic network to be valid as soon as the input register becomes transparent, i.e., at the beginning of each first phase; othewise the data would not arrive soon enough at the crosspoint driver transistors of the AND plane, particularly in view of the propagation delays along the paths from the input register to these crosspoint drivers. And further, because of inherent propagation delays in the feedback lines, the additional processing capability was thus limited to an amount corresponding to a propagation delay of less than the duration of a single clock phase, if the processing is done by the relatively slow static logic. On the other hand, in certain systems it is desirable to add more data processing capability, such as a multistage logic network, having a propagation delay corresponding to more than only a single phase, that is, to insert a multistage logic network having a plurality of successive stages (a plurality of successive logic gates in tandem). Such a multistage logic network, however, has a propagation time delay for new data propagating therethrough which is longer than that of the OR plane, and can be even longer than the duration of a transparent phase of the output register. Such a desired longer propagation delay for the added logic network makes it very difficult to insert the added logic network into the PLA in this manner unless the duration of each of the mutually equal phases is prolonged and hence the speed of operation is undesirably slowed down.